1. Field of the Invention
The present invention relates to semiconductor memory devices, and in particular to a semiconductor memory device having a memory cell array structure containing minute memory cells and metal wiring.
2. Related Art
A process of forming wiring portions in a conventional semiconductor memory device will be described below with reference to FIGS. 9A to 11. FIGS. 9A to 10B are sectional views showing the steps of a process of forming a metal wiring portion of a memory cell. First, an interlayer dielectric film 22 having flat surface and having a thickness of 500 nm is formed on, for example, a main surface of a p-type silicon semiconductor substrate 21 (FIG. 9A). Next, a photoresist is applied to the entire surface of the interlayer dielectric film 22, and a desired resist pattern (not shown) is formed using the photolithography techniques. Thereafter, dry etching, e.g., RIE (Reactive Ion Etching), of the interlayer dielectric film 22 is performed to form grooves having a depth of, e.g., 100 nm in the interlayer dielectric film 22. Then, metal wiring having a laminated structure is formed, the laminated structure including, from lower to upper layers, a Ti layer having a thickness of 50 nm, a TiN layer having a thickness of 50 nm, and a W layer having a thickness of 250 nm. Subsequently, the surface thereof is flattened through CMP (Chemical Mechanical Polishing) to obtain a desired height, to form tungsten wiring 23 in the grooves (FIG. 9B). The tungsten wiring 23 connects to a diffusion layer in the substrate via contacts (not shown).
Next, an interlayer dielectric film 24 having a thickness of 500 nm is formed over the entire surface of the interlayer dielectric film 22 and the tungsten wiring 23. Then, a photoresist is applied to the entire surface of the interlayer dielectric film 24, a resist pattern (not shown) having openings above the part of the tungsten wiring 23 is formed using the photo lithography techniques, and the interlayer dielectric film 24 is patterned using the dry etching techniques, thereby forming via holes having a depth of 500 nm through the interlayer dielectric film 24, the via holes reaching the tungsten wiring 23. Thereafter, a metal layer having a laminated structure including, from lower to upper layers, a Ti layer having a thickness of 50 nm, a TiN layer having a thickness of 50 nm, and a W layer having a thickness of 250 nm is formed so as to fill in the via holes. Then, the surface of the metal layer is flattened through CMP (Chemical Mechanical Polishing) to obtain a desired height to form tungsten plugs 25 in the via holes (FIG. 9C).
Then, a metal wiring layer 26 having a laminated structure including a barrier metal layer 26a having a Ti layer having a thickness of 50 nm and a TiN layer having a thickness of 50 nm, an Al layer 26b having a thickness of 200 nm, and a barrier metal layer 26c having a Ti layer having a thickness of 50 nm and a TiN layer having a thickness of 50 nm, is formed so as to cover the interlayer dielectric film 24 and the tungsten plug 25, the order of layers being from lower to upper (FIG. 9D).
Subsequently, after a photoresist is applied to the metal wiring layer 26 and a desired resist pattern is formed using the photolithography techniques, the dry etching of the metal wiring layer 26 is performed, thereby forming metal wiring lines 26A at a desired position on the tungsten plugs 25 (FIG. 10A). Thereafter, a protection layer 29 is formed on the metal wiring lines 26A (FIG. 10B), thereby completing a part of the multi-layer wiring of the semiconductor memory device. FIG. 11 shows a plan view of the semiconductor memory device before the protection layer 29 is formed, i.e., the plan view of the semiconductor memory device shown in FIG. 10A omitting the interlayer dielectric film 24.
In the design of semiconductor memory device, the wiring, in particular the wiring used for word lines and bit lines, should be formed using a minimum design size. As the size of memory cells is decreased, the size of wiring should be decreased. However, as shown in FIG. 12, it is known that the electromigration (hereinafter referred to as “EM”) characteristics, which show characteristics of metal wiring, are dependent on the wiring size, resulting in that in an area including finer wiring, the more the size of wiring is decreased, the more easily a failure occurs in the wiring. Therefore, there is a problem in that if memory cells are miniaturized to a great degree, it is likely that the reliability of metal wiring diminishes as well.
Another problem of the miniaturization is that, as shown in FIG. 13, the increase in the resistance R of the wiring and in the wiring capacitance C leads to an increase in the time constant τ(=C×R), resulting in the delay of signals. Here, the wiring capacitance means the capacitance between adjacent wiring lines. Since a delay occurring in a signal line for transmitting signals causes changes in the driving of a transistor, which should operate at a high speed, the device performance may be affected.
A semiconductor memory device aiming to decrease the coupling capacitance between bit lines in order to decrease malfunctions is disclosed in Japanese Patent Laid-Open Publication No. 2002-57227. Each bit line of the semiconductor memory device has an upper wiring portion and a lower wiring portion, and the mutually adjacent portions of the respectively adjacent two bit lines are provided in different layers from each other.